1. Field of the Invention
This invention relates to phase lock loop systems and more particularly to voltage controlled oscillators thereof of the type having an input controller.
2. Description of the Prior Art
It is known to use phase lock loops (PLLs), also referred to in the art as phase locked loops, for various applications. One such application is to use a PLL as a frequency multiplier. For example, the multiple high speed on-the-fly impact line printer apparatus described in the aforementioned Carrington et al patent, which is incorporated herein by reference, employs a PLL as a frequency multiplier in the print hammer control system to generate the subscan pulses from the scan pulses used in the system. In the Carrington et al application, the aforementioned PLL is referred to therein as a phase lock loop oscillator circuit. The circuit is designated therein with the reference numeral 22 and shown schematically in block form in the accompanying drawing thereof.
The PLL oscillator circuit converts the printer scan pulses to the required number of subscan pulses which are used in the operation of the printer apparatus in accordance with the scan/subscan principle of operation well known to those skilled in the art. The principle is based on the pitch differential between the print hammer spacing and the type element spacing, cf. U.S. Pat. No. 4,275,653, also incorporated by reference herein. As such, each scan pulse is converted into a number of subscan pulses that is a fixed multiple correlated with the particular pitch differential. For the pitch differential example given in the Carrington et al application, the PLL generates subscan pulses at the rate of four subscan pulses per scan pulse. This rate of conversion is constant regardless of the speed of the printer type element band. However, while the rate is constant, the scan frequency, i.e number of scan pulses per second, is dependent on the speed of the type element band. Thus, the subscan pulses are generated by the PLL oscillator circuit at subscan frequency, i.e. the number of subscan pulses per second, which is equivalent to the product of the aforementioned multiple and scan frequency.
A PLL voltage control oscillator (VCO) circuit is described in the aforementioned Call patent, which is also incorporated by reference herein. The VCO of the Call PLL includes a current controlled oscillator (ICO) and an input controller coupled in series to the ICO. The ICO is substantially identical to a conventional VCO except that it is controlled by current instead of by voltage as is done in conventional VCOs. Accordingly, whereas in a conventional PLL the error voltage is fed directly into the VCO, in the Call PLL the error voltage is processed by the input controller prior to its application to the ICO. For sake of explanation and clarity, some of the Call patent elements discussed hereinafter are also sometimes herein identified parenthetically with their corresponding reference characters as used in the Call patent so as to distinguish them from the reference characters of the present application.
The input controller of Call includes two current mirrors (designated therein by the respective reference numerals 56 and 64) which provide respective output currents (designated therein as Ifr and Igain, respectively). The output current (Ifr) from the one current mirror (56) sets a frequency referred to therein as the free-run center, i.e. midpoint, frequency of the ICO. The output current from the other current mirror (64) sets the desired gain Kv of the ICO. The current mirrors (56, 64) are connected to external circuits (designated therein by the respective reference numerals 54 and 60) and each of which allows the output current of the particular current mirror to which it is connected to be adjusted.
The external circuit (54), which is associated with the current mirror (56) that provides the output current (Ifr), includes two mutually exclusive reference sources, one of which is a resistor coupled to ground or other reference potential, and the other of which is a current source. One of the two sources is selectively coupled to one of the two legs of the current mirror (56), the other leg of which provides the aforementioned output current (Ifr) and is the output leg of the current mirror (56).
The external circuit (60), which is associated with the other current mirror (64), has a similar configuration. It includes two mutually exclusive reference sources, one of which is a resistor coupled to the error voltage (Vo) terminal of the associated PLL or a voltage (Vin) derived therefrom, and the other of which is coupled to a current source (Iin) which is a function of the PLL error voltage. One of the two sources is selectively coupled to one of the two legs of the current mirror (64), the other leg of which provides the aforementioned output current (Igain) and is the output leg of the current mirror (64).
The two current mirrors (56, 64) are configured in a summing difference mode. More specifically, the transistors of the current mirror (56), which produces the output current (Ifr), are of one type and the transistors of the other current mirror (64) are of the complementary type. In the preferred embodiment, the transistors of current mirror (56) are PNPs and those of current mirror (64) are NPNs. The respective output legs of the current mirrors are connected at a summing difference node (designated therein by the reference number 66), which in turn is connected to the ICO so as to adjust independently the gain and free-run frequency of the ICO. More specifically, with this configuration, the current (Ifr) flows toward the node (66) and the current (Igain) flows away from node (66) and the resultant control current (Ifr - Igain), i.e. Ifr minus Igain, flows in a direction away from node (66) and towards the ICO.
It was found that the Call PLL had certain characteristics that were not amenable or desirable for its direct implementation in certain applications where the error voltage must be adjusted by the PLL to maintain the same and/or precise ICO frequency, such as in certain frequency tracking applications, for example. For one thing, when the error voltage (Vo) of the Call PLL is at its median voltage, the VCO and more particularly the ICO thereof oscillates at its center frequency (Ffr). As a result, any change in gain causes a shift in the center frequency error voltage (Vo) in the PLL in order to maintain the same ICO center frequency in the PLL resulting in a non-symmetric frequency range control which adversely affects the operation of the PLL for these particular type of applications. This is particularly true in the case of the aforedescribed Carrington et al multispeed printer apparatus. Since each individual speed used by the printer is correlated with a particular center frequency of the VCO, any undesired shift in the center frequency error voltage in the PLL in order to maintain the same center frequency results in a non-symmetric frequency range about the desired center frequency resulting in an asymmetric frequency range control that adversely affects the generation of the subscan pulses and therefore the operation of the printer. Because of these and other characteristics, the Call PLL is hence not conducive for direct implementation in certain applications such as, for example, the multispeed printer apparatus of Carrington et al, and would require extensive modification to make it amenable for such applications thereby increasing the circuit complexity and cost.